%0 Conference Paper %1 conf/apsec/DasKC06 %A Das, Dipankar %A Kumar, Rajeev %A Chakrabarti, P. P. %B APSEC %D 2006 %I IEEE Computer Society %K dblp %P 199-208 %T Timing Verification of UML Activity Diagram Based Code Block Level Models for Real Time Multiprocessor System-on-Chip Applications. %U http://dblp.uni-trier.de/db/conf/apsec/apsec2006.html#DasKC06 %@ 0-7695-2685-3

@inproceedings{conf/apsec/DasKC06, added-at = {2023-03-23T00:00:00.000+0100}, author = {Das, Dipankar and Kumar, Rajeev and Chakrabarti, P. P.}, biburl = {https://www.bibsonomy.org/bibtex/23057b4faaaa83832c01ef9420ece892e/dblp}, booktitle = {APSEC}, crossref = {conf/apsec/2006}, ee = {https://doi.ieeecomputersociety.org/10.1109/APSEC.2006.56}, interhash = {37ea204985233fc6b85783702fc9d262}, intrahash = {3057b4faaaa83832c01ef9420ece892e}, isbn = {0-7695-2685-3}, keywords = {dblp}, pages = {199-208}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T09:46:05.000+0200}, title = {Timing Verification of UML Activity Diagram Based Code Block Level Models for Real Time Multiprocessor System-on-Chip Applications.}, url = {http://dblp.uni-trier.de/db/conf/apsec/apsec2006.html#DasKC06}, year = 2006 }