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Scenario preprocessing approach for the reconfiguration of fault-tolerant NoC-based MPSoCs
MICROPROCESSORS AND MICROSYSTEMS, (2016)
DOI: 10.1016/j.micpro.2015.08.005
Аннотация
The latest technologies of integrated circuit manufacturing allow
billions of transistors to be arranged on a single chip, enabling the
chip to implement a complex parallel system, which requires a
communications architecture that has high scalability and a high degree
of parallelism, such as a Network-on-Chip (NoC). These technologies are
very close to the physical limitations, which increases the faults in
manufacturing and at runtime. Therefore, it is essential to provide a
method for fault recovery that would enable the NoC to operate in the
presence of faults and still ensure deadlock-free routing. The
preprocessing of the most probable fault scenarios enables us to
anticipate the calculation of deadlock-free routings, reducing the time
that is necessary to interrupt the system during a fault occurrence.
This work proposes a technique that employs the preprocessing of fault
scenarios based on forecasting fault tendencies, which is performed with
a fault threshold circuit operating in accordance with high-level
software. We propose methods for dissimilarity analysis of scenarios
based on cross-correlation measurements of link fault matrices.
Experimental results employing RTL simulation with synthetic traffic
prove the quality of the analytic metrics that are used to select the
preprocessed scenarios. Furthermore, the experiments show the efficacy
and efficiency of the proposed dissimilarity methods, quantifying the
latency penalization when using the coverage scenarios approach. (C)
2015 Elsevier B.V. All rights reserved.
