%0 Journal Article %1 journals/jssc/OzdemirKPLC96 %A Özdemir, Hakan %A Kepkep, Asim %A Pamir, Banu %A Leblebici, Yusuf %A Çilingiroglu, Ugur %D 1996 %J IEEE J. Solid State Circuits %K dblp %N 8 %P 1141-1150 %T A capacitive threshold-logic gate. %U http://dblp.uni-trier.de/db/journals/jssc/jssc31.html#OzdemirKPLC96 %V 31

@article{journals/jssc/OzdemirKPLC96, added-at = {2022-07-18T00:00:00.000+0200}, author = {Özdemir, Hakan and Kepkep, Asim and Pamir, Banu and Leblebici, Yusuf and Çilingiroglu, Ugur}, biburl = {https://www.bibsonomy.org/bibtex/2269afa731216083da490ab916ee0363c/dblp}, ee = {https://doi.org/10.1109/4.508261}, interhash = {3d83bfd7be0b377cf2186f1a92d6f0aa}, intrahash = {269afa731216083da490ab916ee0363c}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 8, pages = {1141-1150}, timestamp = {2024-04-08T10:42:55.000+0200}, title = {A capacitive threshold-logic gate.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc31.html#OzdemirKPLC96}, volume = 31, year = 1996 }