%0 Conference Paper %1 conf/vlsic/LeeYHCKCLC12 %A Lee, Robin %A Yang, Jung-Ping %A Huang, Chia-En %A Chiu, Chih-Chieh %A Kao, Wei-Shuo %A Cheng, Hong-Chen %A Liao, Hong-Jen %A Chang, Jonathan %B VLSIC %D 2012 %I IEEE %K dblp %P 64-65 %T A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#LeeYHCKCLC12 %@ 978-1-4673-0848-9

@inproceedings{conf/vlsic/LeeYHCKCLC12, added-at = {2016-03-16T00:00:00.000+0100}, author = {Lee, Robin and Yang, Jung-Ping and Huang, Chia-En and Chiu, Chih-Chieh and Kao, Wei-Shuo and Cheng, Hong-Chen and Liao, Hong-Jen and Chang, Jonathan}, biburl = {https://www.bibsonomy.org/bibtex/2357f9dcffba37aacf0739c0845e397a9/dblp}, booktitle = {VLSIC}, crossref = {conf/vlsic/2012}, ee = {http://dx.doi.org/10.1109/VLSIC.2012.6243791}, interhash = {4059a15388ae34f1f4edfef81936cb3e}, intrahash = {357f9dcffba37aacf0739c0845e397a9}, isbn = {978-1-4673-0848-9}, keywords = {dblp}, pages = {64-65}, publisher = {IEEE}, timestamp = {2016-03-17T11:44:28.000+0100}, title = {A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#LeeYHCKCLC12}, year = 2012 }