Abstract
The leakage power can dominate the system power
dissipation and determine the battery life in battery-operated
applications with low duty cycles, such as the wireless sensors,
cellular phones, PDAs or pacemakers. Driven by the need of
ultra-low power applications, this paper presents single ended
6T SRAM (static random access memory) cell which is also
radiation hardened due to maximum use of PMOS
transistors. Due to process imperfection, starting from the 65
nm technology node, device scaling no longer delivers the
power gains. Since then the supply voltage has remained
almost constant and improvement in dynamic power has
stagnated, while the leakage currents have continued to
increase. Therefore, power reduction is the major area of
concern in today’s circuit with minimum-geometry devices
such as nanoscale memories. The proposed design in this
paper saves dynamic write power more than 50%. It also
offers 29.7% improvement in TWA (write access time), 38.5%
improvement in WPWR (write power), 69.6% improvement in
WEDP (write energy delay product), 26.3% improvement in
WEDP variability, 5.6% improvement in RPWR (read power) at
the cost of 22.5% penalty in SNM (static noise margin) at
nominal voltage of VDD = 1 V. The tighter spread in write EDP
implies its robustness against process and temperature
variations. Monte Carlo simulation measurements validate
the design at 32 nm technology node
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