%0 Journal Article %1 hope2013design %D 2013 %E Hope, Dr.Martin %J Int. J. on Recent Trends in Engineering and Technology, %K Codes Correcting DRAM Error Synchronous %N 1 %P 6 %T Design and Characterization of SDRAM Controller IP Core with Built In ECC Module %U http://searchdl.org/public/journals/2013/IJRTET/8/2/29.pdf %V 8 %X In modern digital systems large capacity and data transfer rate is required. Synchronous DRAM (SDRAM) became the memory of choice due to its speed, burst access and pipeline features. A Controller is required to provide proper commands for SDRAM initialization, read/write accesses and memory refresh. In semiconductor memories there are chances of errors. To ensure reliable data storage, an error correction and detection scheme is required. This paper describes the architecture design and characterization of SDRAM Controller IP core with built in Error Correcting Codes (ECC) module which is vendor neutral. The design is described using Verilog HDL, simulated using ModelSim and prototyped in Altera® platform FPGA. Resource utilization and power analysis was done using Altera® Quartus II. Hardware test results are obtained from Signal Tap Logic Analyzer.

@article{hope2013design, abstract = {In modern digital systems large capacity and data transfer rate is required. Synchronous DRAM (SDRAM) became the memory of choice due to its speed, burst access and pipeline features. A Controller is required to provide proper commands for SDRAM initialization, read/write accesses and memory refresh. In semiconductor memories there are chances of errors. To ensure reliable data storage, an error correction and detection scheme is required. This paper describes the architecture design and characterization of SDRAM Controller IP core with built in Error Correcting Codes (ECC) module which is vendor neutral. The design is described using Verilog HDL, simulated using ModelSim and prototyped in Altera® platform FPGA. Resource utilization and power analysis was done using Altera® Quartus II. Hardware test results are obtained from Signal Tap Logic Analyzer.}, added-at = {2014-02-03T07:48:12.000+0100}, biburl = {https://www.bibsonomy.org/bibtex/211f85323be4970a282566dd10f93196b/idescitation}, editor = {Hope, Dr.Martin}, interhash = {4cc08fd6d45264d6117a0bda01d85c4b}, intrahash = {11f85323be4970a282566dd10f93196b}, journal = {Int. J. on Recent Trends in Engineering and Technology,}, keywords = {Codes Correcting DRAM Error Synchronous}, month = {January}, number = 1, pages = 6, timestamp = {2014-02-03T07:48:12.000+0100}, title = {Design and Characterization of SDRAM Controller IP Core with Built In ECC Module}, url = {http://searchdl.org/public/journals/2013/IJRTET/8/2/29.pdf}, volume = 8, year = 2013 }