%0 Journal Article %1 journals/jssc/PelleranoMP09 %A Pellerano, Stefano %A Madoglio, Paolo %A Palaskas, Yorgos %D 2009 %J IEEE J. Solid State Circuits %K dblp %N 12 %P 3422-3433 %T A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#PelleranoMP09 %V 44

@article{journals/jssc/PelleranoMP09, added-at = {2020-08-30T00:00:00.000+0200}, author = {Pellerano, Stefano and Madoglio, Paolo and Palaskas, Yorgos}, biburl = {https://www.bibsonomy.org/bibtex/29ec8bc533e173680f12e5d2905a30b93/dblp}, ee = {https://doi.org/10.1109/JSSC.2009.2032276}, interhash = {6525279c834226c5640bf8448d7193bd}, intrahash = {9ec8bc533e173680f12e5d2905a30b93}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 12, pages = {3422-3433}, timestamp = {2020-08-31T11:44:24.000+0200}, title = {A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#PelleranoMP09}, volume = 44, year = 2009 }