%0 Journal Article %1 journals/vlsisp/RichterF05 %A Richter, Thomas %A Fettweis, Gerhard P. %D 2005 %J VLSI Signal Processing %K %N 1-2 %P 161-173 %T Interleaving on Parallel DSP Architectures. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp39.html#RichterF05 %V 39

@article{journals/vlsisp/RichterF05, added-at = {2023-12-13T01:36:32.000+0100}, author = {Richter, Thomas and Fettweis, Gerhard P.}, biburl = {https://www.bibsonomy.org/bibtex/2d9e4496eb0841f92dc19f3ce9cdc0380/admin}, ee = {https://doi.org/10.1023/B:VLSI.0000047278.94280.c3}, interhash = {73eb9e150d9867a4698e210458301081}, intrahash = {d9e4496eb0841f92dc19f3ce9cdc0380}, journal = {VLSI Signal Processing}, keywords = {}, number = {1-2}, pages = {161-173}, timestamp = {2023-12-13T01:36:32.000+0100}, title = {Interleaving on Parallel DSP Architectures.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp39.html#RichterF05}, volume = 39, year = 2005 }