Article,

Automatic test generation for verifying microprocessors

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IEEE Potentials, 24 (1): 34--37 (February 2005)
DOI: doi:10.1109/MP.2005.1405800

Abstract

A pipelined processor with a high-level behavioural HDL description is presented in this paper. It generates a set of effective test programs by using a simulator, which is able to evaluate with respect to an RTL coverage metric. The proposed optimiser is based on a technique called microGP, an evolutionary system able to automatically device and optimizes the program written in an assembly language. Quantitative coverage measurement presented will guide the test-program generation. The approach is fully automatic and broadly applicable. The minimal test set with the programmable coverage is attained.

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