%0 Conference Paper %1 conf/date/RanjanVASVG04 %A Ranjan, Mukesh %A Verhaegen, Wim %A Agarwal, Anuradha %A Sampath, Hemanth %A Vemuri, Ranga %A Gielen, Georges G. E. %B DATE %D 2004 %I IEEE Computer Society %K dblp %P 604-609 %T Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. %U http://dblp.uni-trier.de/db/conf/date/date2004-1.html#RanjanVASVG04 %@ 0-7695-2085-5

@inproceedings{conf/date/RanjanVASVG04, added-at = {2023-03-24T00:00:00.000+0100}, author = {Ranjan, Mukesh and Verhaegen, Wim and Agarwal, Anuradha and Sampath, Hemanth and Vemuri, Ranga and Gielen, Georges G. E.}, biburl = {https://www.bibsonomy.org/bibtex/26af946103a90cb3a41d7022be348eb5a/dblp}, booktitle = {DATE}, crossref = {conf/date/2004}, ee = {http://dl.acm.org/citation.cfm?id=969054}, interhash = {75d668dc2cef6d169e7488659c1a3c66}, intrahash = {6af946103a90cb3a41d7022be348eb5a}, isbn = {0-7695-2085-5}, keywords = {dblp}, pages = {604-609}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T06:51:35.000+0200}, title = {Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.}, url = {http://dblp.uni-trier.de/db/conf/date/date2004-1.html#RanjanVASVG04}, year = 2004 }