Abstract
We present results on the application of a new
methodology based on Parallel and Distributed Genetic
Programming (PADGP). The aim for the methodology we
present is to automatically perform the placement and
routing of circuits on reconfigurable hardware. The
system has been successfully applied to some benchmark
problems. For each of the problems we have dealt with,
the methodology is capable of finding several
solutions. The results show the methodology's
feasibility for addressing the problem of placement and
routing on FPGAs.
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