%0 Conference Paper %1 conf/islped/SirisantanaCDKR01 %A Sirisantana, Naran %A Cao, Aiqun %A Davidson, Shawn %A Koh, Cheng-Kok %A Roy, Kaushik %B ISLPED %D 2001 %E Macii, Enrico %E De, Vivek %E Irwin, Mary Jane %I ACM %K dblp %P 267-270 %T Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. %U http://dblp.uni-trier.de/db/conf/islped/islped2001.html#SirisantanaCDKR01 %@ 1-58113-371-5

@inproceedings{conf/islped/SirisantanaCDKR01, added-at = {2018-11-06T00:00:00.000+0100}, author = {Sirisantana, Naran and Cao, Aiqun and Davidson, Shawn and Koh, Cheng-Kok and Roy, Kaushik}, biburl = {https://www.bibsonomy.org/bibtex/23ed55dbf246bcdd10898663868fde2f5/dblp}, booktitle = {ISLPED}, crossref = {conf/islped/2001}, editor = {Macii, Enrico and De, Vivek and Irwin, Mary Jane}, ee = {https://doi.org/10.1145/383082.383160}, interhash = {7dd82bcf6f5e80fb03412bbd7c2e7c06}, intrahash = {3ed55dbf246bcdd10898663868fde2f5}, isbn = {1-58113-371-5}, keywords = {dblp}, pages = {267-270}, publisher = {ACM}, timestamp = {2018-11-07T16:25:26.000+0100}, title = {Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.}, url = {http://dblp.uni-trier.de/db/conf/islped/islped2001.html#SirisantanaCDKR01}, year = 2001 }