%0 Journal Article %1 noauthororeditor %A Abbas, S. Syed Ameer %A Mary, M. Beril Sahaya %A Nisha, J. Rahumath %A Thiruvengadam, S. J. %D 2013 %J International Journal of Next-Generation Networks (IJNGN) %K networks wireless %N 1 %P 20 %T Implementation of Pipelined Architecture for Physical Downlink Channels of 3GPPLTE %U https://airccse.org/journal/ijngn/papers/5113ijngn01.pdf %V 5 %X LTE (Long Term Evolution) is a high data rate, low latency and packet optimized radio access technology designed to support roaming Internet access via cell phones and handheld devices in 3G and 4G networks. This paper mainly focuses on to improve the processing speed and decrease the maximum delay of the downlink channels using the pipelined buffer controlled technique. This paper proposes Pipelined buffer controlled Architecture for both transmitter and receiver for Physical Downlink channels of 3GPP-LTE. The transmitter architecture comprises Bit Scrambling, Modulation mapping, Layer mapping, Precoding and Resource element mapping modules. The receiver architecture comprises Demapping from resource elements, Decoding, Comparing and Detection, Delayer mapping and Descrambling modules as described in LTE specifications. In addition to these, buffers are included in both transmitter and receiver architectures. Modelsim is used for simulation, synthesis and implementation are achieved using PlanAhead13.2 tool on Virtex-5, xc5vlx50tff1136-1 device board is used. Implemented results are discussed in terms of RTL design, FPGA editor, Power estimation and Resource estimation.

@article{noauthororeditor, abstract = {LTE (Long Term Evolution) is a high data rate, low latency and packet optimized radio access technology designed to support roaming Internet access via cell phones and handheld devices in 3G and 4G networks. This paper mainly focuses on to improve the processing speed and decrease the maximum delay of the downlink channels using the pipelined buffer controlled technique. This paper proposes Pipelined buffer controlled Architecture for both transmitter and receiver for Physical Downlink channels of 3GPP-LTE. The transmitter architecture comprises Bit Scrambling, Modulation mapping, Layer mapping, Precoding and Resource element mapping modules. The receiver architecture comprises Demapping from resource elements, Decoding, Comparing and Detection, Delayer mapping and Descrambling modules as described in LTE specifications. In addition to these, buffers are included in both transmitter and receiver architectures. Modelsim is used for simulation, synthesis and implementation are achieved using PlanAhead13.2 tool on Virtex-5, xc5vlx50tff1136-1 device board is used. Implemented results are discussed in terms of RTL design, FPGA editor, Power estimation and Resource estimation.}, added-at = {2024-05-10T13:27:20.000+0200}, author = {Abbas, S. Syed Ameer and Mary, M. Beril Sahaya and Nisha, J. Rahumath and Thiruvengadam, S. J.}, biburl = {https://www.bibsonomy.org/bibtex/2d1640af99fe487830b1e039434f369cf/josephjonse}, interhash = {7fed13976aed0a19ad366f223b80b052}, intrahash = {d1640af99fe487830b1e039434f369cf}, issn = {ISSN : 0975-7023 Online); 0975-7252 ( Print )}, journal = {International Journal of Next-Generation Networks (IJNGN)}, keywords = {networks wireless}, language = {English}, month = {3}, number = 1, pages = 20, timestamp = {2024-05-10T13:27:20.000+0200}, title = {Implementation of Pipelined Architecture for Physical Downlink Channels of 3GPPLTE}, url = {https://airccse.org/journal/ijngn/papers/5113ijngn01.pdf}, volume = 5, year = 2013 }