%0 Conference Paper %1 conf/vlsit/OsadaNNLWLFLC23 %A Osada, Yoshiaki %A Nakazato, Takaaki %A Nii, Koji %A Liaw, Jhon-Jhy %A Wu, Shien-Yang Michael %A Li, Quincy %A Fujiwara, Hidehiro %A Liao, Hung-Jen %A Chang, Tsung-Yung Jonathan %B VLSI Technology and Circuits %D 2023 %I IEEE %K dblp %P 1-2 %T 3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#OsadaNNLWLFLC23 %@ 978-4-86348-806-9

@inproceedings{conf/vlsit/OsadaNNLWLFLC23, added-at = {2023-07-28T00:00:00.000+0200}, author = {Osada, Yoshiaki and Nakazato, Takaaki and Nii, Koji and Liaw, Jhon-Jhy and Wu, Shien-Yang Michael and Li, Quincy and Fujiwara, Hidehiro and Liao, Hung-Jen and Chang, Tsung-Yung Jonathan}, biburl = {https://www.bibsonomy.org/bibtex/2302da806b91357cc1becb3236faf12e4/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2023}, ee = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185289}, interhash = {91aa349adf04d8d2f418631b48b8bacf}, intrahash = {302da806b91357cc1becb3236faf12e4}, isbn = {978-4-86348-806-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T19:13:01.000+0200}, title = {3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications.}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#OsadaNNLWLFLC23}, year = 2023 }