%0 Journal Article %1 journals/ieicet/MiyakoshiMIKY06 %A Miyakoshi, Junichi %A Murachi, Yuichiro %A Ishihara, Tomokazu %A Kawaguchi, Hiroshi %A Yoshimoto, Masahiko %D 2006 %J IEICE Trans. Electron. %K dblp %N 11 %P 1629-1636 %T A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet89c.html#MiyakoshiMIKY06 %V 89-C

@article{journals/ieicet/MiyakoshiMIKY06, added-at = {2024-03-11T00:00:00.000+0100}, author = {Miyakoshi, Junichi and Murachi, Yuichiro and Ishihara, Tomokazu and Kawaguchi, Hiroshi and Yoshimoto, Masahiko}, biburl = {https://www.bibsonomy.org/bibtex/2288ca36cb9d9f696cf34caeacfa9e5c8/dblp}, ee = {https://doi.org/10.1093/ietele/e89-c.11.1629}, interhash = {973531b0a1766c08cc78234e5f70e0ed}, intrahash = {288ca36cb9d9f696cf34caeacfa9e5c8}, journal = {IEICE Trans. Electron.}, keywords = {dblp}, number = 11, pages = {1629-1636}, timestamp = {2024-04-08T15:47:38.000+0200}, title = {A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet89c.html#MiyakoshiMIKY06}, volume = {89-C}, year = 2006 }