%0 Conference Paper %1 conf/vlsic/LeeVTV21 %A Lee, Jinseok %A Valavi, Hossein %A Tang, Yinqi %A Verma, Naveen %B VLSI Circuits %D 2021 %I IEEE %K dblp %P 1-2 %T Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#LeeVTV21 %@ 978-4-86348-780-2

@inproceedings{conf/vlsic/LeeVTV21, added-at = {2021-08-02T00:00:00.000+0200}, author = {Lee, Jinseok and Valavi, Hossein and Tang, Yinqi and Verma, Naveen}, biburl = {https://www.bibsonomy.org/bibtex/2e88d3aba0607184e77310157426dd1fc/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2021}, ee = {https://doi.org/10.23919/VLSICircuits52068.2021.9492444}, interhash = {98ba21d85c1b6a6419ede170c2530b8f}, intrahash = {e88d3aba0607184e77310157426dd1fc}, isbn = {978-4-86348-780-2}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T21:13:43.000+0200}, title = {Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#LeeVTV21}, year = 2021 }