%0 Journal Article %1 journals/tvlsi/ChakrabortyR12 %A Chakraborty, Koushik %A Roy, Sanghamitra %D 2012 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 3 %P 512-522 %T Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi20.html#ChakrabortyR12 %V 20

@article{journals/tvlsi/ChakrabortyR12, added-at = {2022-10-02T00:00:00.000+0200}, author = {Chakraborty, Koushik and Roy, Sanghamitra}, biburl = {https://www.bibsonomy.org/bibtex/2118393a972bf2e817d835b6fbda9e178/dblp}, ee = {https://doi.org/10.1109/TVLSI.2011.2105513}, interhash = {9b5bb327f433a9b2942f0f46efc79cf1}, intrahash = {118393a972bf2e817d835b6fbda9e178}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 3, pages = {512-522}, timestamp = {2024-04-08T14:32:31.000+0200}, title = {Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi20.html#ChakrabortyR12}, volume = 20, year = 2012 }