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%0 Journal Article
%1 journals/jssc/DoYVLYK14
%A Do, Anh-Tuan
%A Yin, Chun
%A Velayudhan, Kavitha
%A Lee, Zhao Chuan
%A Yeo, Kiat Seng
%A Kim, Tony Tae-Hyoung
%D 2014
%J IEEE J. Solid State Circuits
%K dblp
%N 7
%P 1487-1498
%T 0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc49.html#DoYVLYK14
%V 49
@article{journals/jssc/DoYVLYK14,
added-at = {2021-07-25T00:00:00.000+0200},
author = {Do, Anh-Tuan and Yin, Chun and Velayudhan, Kavitha and Lee, Zhao Chuan and Yeo, Kiat Seng and Kim, Tony Tae-Hyoung},
biburl = {https://www.bibsonomy.org/bibtex/2066a6c8328641926dd1ee090b42b56a9/dblp},
ee = {https://doi.org/10.1109/JSSC.2014.2316241},
interhash = {9f2e0c7bf2ce245d1f49ab0cb0ffbd93},
intrahash = {066a6c8328641926dd1ee090b42b56a9},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 7,
pages = {1487-1498},
timestamp = {2024-04-08T10:43:09.000+0200},
title = {0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc49.html#DoYVLYK14},
volume = 49,
year = 2014
}
