%0 Conference Paper %1 conf/vlsid/PomeranzR10a %A Pomeranz, Irith %A Reddy, Sudhakar M. %B VLSI Design %D 2010 %I IEEE Computer Society %K dblp %P 39-44 %T Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#PomeranzR10a %@ 978-0-7695-3928-7

@inproceedings{conf/vlsid/PomeranzR10a, added-at = {2023-03-24T00:00:00.000+0100}, author = {Pomeranz, Irith and Reddy, Sudhakar M.}, biburl = {https://www.bibsonomy.org/bibtex/2d0e66f2f406a460db03cda3c5d74bf21/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2010}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.16}, interhash = {9fe8e03899429ee970833c6348820a7e}, intrahash = {d0e66f2f406a460db03cda3c5d74bf21}, isbn = {978-0-7695-3928-7}, keywords = {dblp}, pages = {39-44}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:17:37.000+0200}, title = {Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#PomeranzR10a}, year = 2010 }