%0 Conference Paper %1 conf/glvlsi/ZhouHLZD17 %A Zhou, Chaobing %A Huang, Libo %A Li, Zhisheng %A Zhang, Tan %A Dou, Qiang %B ACM Great Lakes Symposium on VLSI %D 2017 %E Behjat, Laleh %E Han, Jie %E Velev, Miroslav N. %E Chen, Deming %I ACM %K dblp %P 281-286 %T Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2017.html#ZhouHLZD17 %@ 978-1-4503-4972-7

@inproceedings{conf/glvlsi/ZhouHLZD17, added-at = {2018-11-06T00:00:00.000+0100}, author = {Zhou, Chaobing and Huang, Libo and Li, Zhisheng and Zhang, Tan and Dou, Qiang}, biburl = {https://www.bibsonomy.org/bibtex/2bb0f945c4f93101345f49f83e52cbe2b/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2017}, editor = {Behjat, Laleh and Han, Jie and Velev, Miroslav N. and Chen, Deming}, ee = {https://doi.org/10.1145/3060403.3060423}, interhash = {b20f8b90a19227f48c4d47ef2a7e912e}, intrahash = {bb0f945c4f93101345f49f83e52cbe2b}, isbn = {978-1-4503-4972-7}, keywords = {dblp}, pages = {281-286}, publisher = {ACM}, timestamp = {2018-11-07T13:01:39.000+0100}, title = {Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2017.html#ZhouHLZD17}, year = 2017 }