%0 Journal Article %1 IJACSA.2012.031227 %A Rashmi A Jain, Dr. Dinesh V Padole %D 2012 %J International Journal of Advanced Computer Science and Applications(IJACSA) %K (CMP).,Flexible (FMC); Core Heterogeneous Multi and chip instruction level memory-level multiprocessors parallelism parallelism; scalable; system thread-level %N 12 %T Scalable and Flexible heterogeneous multi-core system %U http://ijacsa.thesai.org/ %V 3 %X Multi-core system has wide utility in today’s applications due to less power consumption and high performance. Many researchers are aiming at improving the performance of these systems by providing flexible multi-core architecture. Flexibility in the multi-core processors system provides high throughput for uniform parallel applications as well as high performance for more general work. This flexibility in the architecture can be achieved by scalable and changeable-size window micro architecture. It uses the concept of execution locality to provide large-window capabilities. Use of high memory-level parallelism (MLP) reduces the memory wall. Micro architecture contains a set of small and fast cache processors which execute high locality code. A network of small in-order memory engines use low locality code to improve performance by using instruction level parallelism (ILP). Dynamic heterogeneous multi-core architecture is capable of recon?guring itself to ?t application requirements. Study of different scalable and ?exible architectures of heterogeneous multi-core system has been carried out and has been presented.

@article{IJACSA.2012.031227, abstract = {Multi-core system has wide utility in today’s applications due to less power consumption and high performance. Many researchers are aiming at improving the performance of these systems by providing flexible multi-core architecture. Flexibility in the multi-core processors system provides high throughput for uniform parallel applications as well as high performance for more general work. This flexibility in the architecture can be achieved by scalable and changeable-size window micro architecture. It uses the concept of execution locality to provide large-window capabilities. Use of high memory-level parallelism (MLP) reduces the memory wall. Micro architecture contains a set of small and fast cache processors which execute high locality code. A network of small in-order memory engines use low locality code to improve performance by using instruction level parallelism (ILP). Dynamic heterogeneous multi-core architecture is capable of recon?guring itself to ?t application requirements. Study of different scalable and ?exible architectures of heterogeneous multi-core system has been carried out and has been presented.}, added-at = {2014-02-21T08:00:08.000+0100}, author = {{Rashmi A Jain}, Dr. Dinesh V Padole}, biburl = {https://www.bibsonomy.org/bibtex/2df77cf5729d07baa83d10cafe9b64496/thesaiorg}, interhash = {b7f1e3ca968efce389d4008c505930c7}, intrahash = {df77cf5729d07baa83d10cafe9b64496}, journal = {International Journal of Advanced Computer Science and Applications(IJACSA)}, keywords = {(CMP).,Flexible (FMC); Core Heterogeneous Multi and chip instruction level memory-level multiprocessors parallelism parallelism; scalable; system thread-level}, number = 12, timestamp = {2014-02-21T08:00:08.000+0100}, title = {{Scalable and Flexible heterogeneous multi-core system}}, url = {http://ijacsa.thesai.org/}, volume = 3, year = 2012 }