%0 Journal Article %1 journals/tvlsi/LingLTSSY21 %A Ling, Ming %A Lin, Qingde %A Tan, Ke %A Shao, Tianxiang %A Shen, Shan %A Yang, Jun %D 2021 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 12 %P 2197-2209 %T A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi29.html#LingLTSSY21 %V 29

@article{journals/tvlsi/LingLTSSY21, added-at = {2022-03-15T00:00:00.000+0100}, author = {Ling, Ming and Lin, Qingde and Tan, Ke and Shao, Tianxiang and Shen, Shan and Yang, Jun}, biburl = {https://www.bibsonomy.org/bibtex/2e48c2131b2d22121d52e3710468ee53d/dblp}, ee = {https://doi.org/10.1109/TVLSI.2021.3120653}, interhash = {bd15551e43c9fe409717454ffbf42d3a}, intrahash = {e48c2131b2d22121d52e3710468ee53d}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 12, pages = {2197-2209}, timestamp = {2024-04-08T14:32:25.000+0200}, title = {A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi29.html#LingLTSSY21}, volume = 29, year = 2021 }