%0 Conference Paper %1 conf/iecon/Zhang0WWK15 %A Zhang, Zhenbin %A Chen, Zhe %A Wang, Fengxiang %A Wu, Chun %A Kennel, Ralph %B IECON %D 2015 %I IEEE %K dblp %P 1282-1287 %T Fully FPGA based performance-enhanced DMPC for grid-tied AFEs with multiple predictions. %U http://dblp.uni-trier.de/db/conf/iecon/iecon2015.html#Zhang0WWK15 %@ 978-1-4799-1762-4

@inproceedings{conf/iecon/Zhang0WWK15, added-at = {2019-05-09T00:00:00.000+0200}, author = {Zhang, Zhenbin and Chen, Zhe and Wang, Fengxiang and Wu, Chun and Kennel, Ralph}, biburl = {https://www.bibsonomy.org/bibtex/2a4b81bb1b0b630614faab3db95713e30/dblp}, booktitle = {IECON}, crossref = {conf/iecon/2015}, ee = {https://doi.org/10.1109/IECON.2015.7392277}, interhash = {beb531405afbcb6104bbee61879a2c21}, intrahash = {a4b81bb1b0b630614faab3db95713e30}, isbn = {978-1-4799-1762-4}, keywords = {dblp}, pages = {1282-1287}, publisher = {IEEE}, timestamp = {2019-10-17T21:27:00.000+0200}, title = {Fully FPGA based performance-enhanced DMPC for grid-tied AFEs with multiple predictions.}, url = {http://dblp.uni-trier.de/db/conf/iecon/iecon2015.html#Zhang0WWK15}, year = 2015 }