%0 Conference Paper %1 conf/anss/HirechFGR94 %A Hirech, Mokhtar %A Florent, Olivier %A Greiner, Alain %A Rejouan, El Housseine %B Annual Simulation Symposium %D 1994 %I IEEE %K dblp %P 255-261 %T Application of a redefinable symbolic simulation technique in VLSI testability design rules checking. %U http://dblp.uni-trier.de/db/conf/anss/anss1994.html#HirechFGR94 %@ 0-8186-5620-4

@inproceedings{conf/anss/HirechFGR94, added-at = {2023-03-24T00:00:00.000+0100}, author = {Hirech, Mokhtar and Florent, Olivier and Greiner, Alain and Rejouan, El Housseine}, biburl = {https://www.bibsonomy.org/bibtex/2d2918d206386f2945caf2c72c084471f/dblp}, booktitle = {Annual Simulation Symposium}, crossref = {conf/anss/1994}, ee = {https://doi.ieeecomputersociety.org/10.1109/SIMSYM.1994.283090}, interhash = {dad2cc05c829db7d5af3c8d749559281}, intrahash = {d2918d206386f2945caf2c72c084471f}, isbn = {0-8186-5620-4}, keywords = {dblp}, pages = {255-261}, publisher = {IEEE}, timestamp = {2024-04-10T13:47:44.000+0200}, title = {Application of a redefinable symbolic simulation technique in VLSI testability design rules checking.}, url = {http://dblp.uni-trier.de/db/conf/anss/anss1994.html#HirechFGR94}, year = 1994 }