Inproceedings,
2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC.
H. Mair, E. Wang, A. Nayak, R. Lagerquist, L. Chou, G. Gammie, H. Chen, L. Yong, M. Rahman, J. Wiedemeier, R. Madhavaram, A. Chiou, B. Li, V. Lin, R. Huang, M. Yanq, A. Thippana, O. Su, and S. Huang.ISSCC, page 50-52. IEEE, (2020)
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- BibTeX key
- conf/isscc/MairWNLCGCYRWMC20
- entry type
- inproceedings
- booktitle
- ISSCC
- year
- 2020
- pages
- 50-52
- publisher
- IEEE
- crossref
- conf/isscc/2020
- ee
- https://doi.org/10.1109/ISSCC19947.2020.9062897
- isbn
- 978-1-7281-3205-1
- url
- http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#MairWNLCGCYRWMC20
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%1 conf/isscc/MairWNLCGCYRWMC20
%A Mair, Hugh
%A Wang, Ericbill
%A Nayak, Ashish
%A Lagerquist, Rolf
%A Chou, Loda
%A Gammie, Gordon
%A Chen, HsinChen
%A Yong, Lee-Kee
%A Rahman, Manzur
%A Wiedemeier, Jenny
%A Madhavaram, Ramu
%A Chiou, Alex
%A Li, Blundt
%A Lin, Vincent
%A Huang, Rory
%A Yanq, Michael
%A Thippana, Achuta
%A Su, Osric
%A Huang, S. A.
%B ISSCC
%D 2020
%I IEEE
%K dblp
%P 50-52
%T 2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#MairWNLCGCYRWMC20
%@ 978-1-7281-3205-1
@inproceedings{conf/isscc/MairWNLCGCYRWMC20,
added-at = {2020-04-18T00:00:00.000+0200},
author = {Mair, Hugh and Wang, Ericbill and Nayak, Ashish and Lagerquist, Rolf and Chou, Loda and Gammie, Gordon and Chen, HsinChen and Yong, Lee-Kee and Rahman, Manzur and Wiedemeier, Jenny and Madhavaram, Ramu and Chiou, Alex and Li, Blundt and Lin, Vincent and Huang, Rory and Yanq, Michael and Thippana, Achuta and Su, Osric and Huang, S. A.},
biburl = {https://www.bibsonomy.org/bibtex/2b913edce9a1ce46fe1158e7bce8bde05/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2020},
ee = {https://doi.org/10.1109/ISSCC19947.2020.9062897},
interhash = {dd9237e7f7cf3d2e220cbe7a0f5366c7},
intrahash = {b913edce9a1ce46fe1158e7bce8bde05},
isbn = {978-1-7281-3205-1},
keywords = {dblp},
pages = {50-52},
publisher = {IEEE},
timestamp = {2020-04-21T11:41:16.000+0200},
title = {2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#MairWNLCGCYRWMC20},
year = 2020
}