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%0 Journal Article
%1 journals/jssc/MadoglioRCPSLP10
%A Madoglio, Paolo
%A Ravi, Ashoke
%A Cuellar, Luis
%A Pellerano, Stefano
%A Seddighrad, Parmoon
%A Lomeli, Ismael
%A Palaskas, Yorgos
%D 2010
%J IEEE J. Solid State Circuits
%K dblp
%N 7
%P 1410-1420
%T A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#MadoglioRCPSLP10
%V 45
@article{journals/jssc/MadoglioRCPSLP10,
added-at = {2020-08-30T00:00:00.000+0200},
author = {Madoglio, Paolo and Ravi, Ashoke and Cuellar, Luis and Pellerano, Stefano and Seddighrad, Parmoon and Lomeli, Ismael and Palaskas, Yorgos},
biburl = {https://www.bibsonomy.org/bibtex/265b37af132cb8e5025077b80c70879fa/dblp},
ee = {https://doi.org/10.1109/JSSC.2010.2048086},
interhash = {e54db63a1134a3d20e94f657a2c71c1e},
intrahash = {65b37af132cb8e5025077b80c70879fa},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 7,
pages = {1410-1420},
timestamp = {2020-08-31T11:41:23.000+0200},
title = {A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#MadoglioRCPSLP10},
volume = 45,
year = 2010
}