Article,
Design styles of Asymmetric nMOS and their Simulation
International Journal on Recent and Innovation Trends in Computing and Communication, 3 (3): 1129--1131 (March 2015)
DOI: 10.17762/ijritcc2321-8169.150352
Abstract
Scaling down of the MOSFET has been done extensively to meet the need for high speed devices. Symmetric MOSFET with LDD structure could not mitigate the short channel effects, as the device was scaled down to deep sub-micrometer regime. Asymmetric MOSFET design styles were thus adopted to achieve increased device speed. In this paper, two asymmetric MOSFETs are designed and simulated using device simulator (SILVACO) - one with LDD at drain side only and second with unequal junction depths.
