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Disambiguation of "Alioto, Massimo"

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Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects.

, and . ISCAS, page 3255-3258. IEEE, (2007)

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Massimo Viola

Massimo Malagó

Massimo Tallarida

Massimo Moser

Massimo Epis

 

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Minimum-Effort Design of Ultra-Low Power Interfaces for the Internet of Things., , and . ICECS, page 105-106. IEEE, (2019)A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS., , , , and . IEEE J. Solid State Circuits, 49 (11): 2462-2473 (2014)Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (5): 737-750 (2011)Evaluation of energy consumption in RC ladder circuits driven by a ramp input., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (10): 1094-1107 (2004)Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators., , , and . ISCAS, page 157-160. IEEE, (2015)Design strategies of cascaded CML gates., and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (2): 85-89 (2006)Low-Energy Voice Activity Detection via Energy-Quality Scaling From Data Conversion to Machine Learning., , and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (4): 1378-1388 (2020)Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits., , , and . ECCTD, page 779-782. IEEE, (2009)Guest Editorial IEEE 2022 European Solid-State Circuits Conference., and . IEEE J. Solid State Circuits, 58 (7): 1823-1824 (2023)Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations., , , , and . ISCAS, page 2043-2046. IEEE, (2011)