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Disambiguation of "Sowa, Masahiro"

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Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.

, , , and . EUC, volume 3824 of Lecture Notes in Computer Science, page 340-349. Springer, (2005)

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Masahiro Noguchi

Masahiro Ogawa

Masahiro Yoshida

Masahiro Katsura

Masahiro Niitsuma

 

Other publications of authors with the same name

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model., , and . EUC, volume 4808 of Lecture Notes in Computer Science, page 196-208. Springer, (2007)Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core., , , and . EUC, volume 3824 of Lecture Notes in Computer Science, page 340-349. Springer, (2005)Hybrid Processor Based on VLIW and PN-Superscalar., and . PDPTA, page 623-632. CSREA Press, (1996)Queue Register File Optimization Algorithm for QueueCore Processor., , and . SBAC-PAD, page 169-176. IEEE Computer Society, (2007)Proposal and Design of a Parallel Queue Processor Architecture (PQP)., , , , and . IASTED PDCS, page 549-554. IASTED/ACTA Press, (2002)An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture., , , and . EUC, volume 3824 of Lecture Notes in Computer Science, page 77-86. Springer, (2005)Compiler-Controlled Parallelism-Independent Scheduling Method for Cluster Computing Systems., and . HPCS, page 182-189. IEEE Computer Society, (2002)Intruction Fetch Mechanism for PN-Superscalar., and . PDPTA, page 1406-1410. CSREA Press, (1997)High Speed Synchronization for a Statically Scheduled Superscalar Processor., and . Int. J. High Speed Comput., 3 (1): 77-87 (1991)Design and implementation of a queue compiler., , and . Microprocess. Microsystems, 33 (2): 129-138 (2009)