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Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors.

, , , , , и . FCCM, стр. 202. IEEE, (2023)

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Lesley Mearns

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A Multiprocessor System-on-Chip Implementation of a Laser-based Transparency Meter on an FPGA., , , и . FPT, стр. 373-376. IEEE, (2007)An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs., и . FPT, стр. 361-364. IEEE, (2008)A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only)., , и . FPGA, стр. 242. ACM, (2014)Using reconfigurability to achieve real-time profiling for hardware/software codesign., и . FPGA, стр. 190-199. ACM, (2004)The routability of multiprocessor network topologies in FPGAs., , и . SLIP, стр. 49-56. ACM, (2006)Standardizing the Performance Assessment of Reconfigurable Processor Architectures., и . FCCM, стр. 282-283. IEEE Computer Society, (2003)Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support., , и . FPL, стр. 224-230. IEEE, (2012)A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification., , , , , и . FPL, стр. 1-6. IEEE, (2006)TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features., и . FPL, стр. 1-4. IEEE, (2017)Leveraging reconfigurability in the hardware/software codesign process., и . ACM Trans. Reconfigurable Technol. Syst., 4 (3): 28:1-28:27 (2011)