( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices.

, , и . FPL, стр. 438-444. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Darren Vaughn Carlson

Anna Vaughn Clissold

Michael Betz

Adolf Betz

Joseph Betz

 

Другие публикации лиц с тем же именем

Timing-driven placement for FPGAs., , и . FPGA, стр. 203-213. ACM, (2000)Automatic generation of FPGA routing architectures from high-level descriptions., и . FPGA, стр. 175-184. ACM, (2000)Are FPGAs suffering from the innovator's dilemna?, и . FPGA, стр. 135-136. ACM, (2013)FPGA challenges and opportunities at 40nm and beyond.. FPL, стр. 4. IEEE, (2009)Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization., и . FPT, стр. 110-117. IEEE, (2018)You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference., , и . ACM Trans. Reconfigurable Technol. Syst., 11 (3): 20:1-20:23 (2018)Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation., и . ACM Trans. Reconfigurable Technol. Syst., 16 (2): 31:1-31:24 (июня 2023)Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs., , и . ACM Trans. Reconfigurable Technol. Syst., 11 (1): 6:1-6:22 (2018)Feel Free to Interrupt: Safe Task Stopping to Enable FPGA Checkpointing and Context Switching., и . ACM Trans. Reconfigurable Technol. Syst., 13 (1): 3:1-3:27 (2020)Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (4): 686-697 (2008)