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A novel floating-gate binary signal to multiple-valued signal converter for multiple-valued CMOS logic., , , , и . ICECS, стр. 579-582. IEEE, (2002)Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware., и . ICES, том 2606 из Lecture Notes in Computer Science, стр. 365-376. Springer, (2003)Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing., , , и . NORCAS, стр. 1-4. IEEE, (2016)Clocked semi-floating-gate ultra low-voltage current mirror., , и . ICECS, стр. 1038-1041. IEEE, (2008)Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology., , и . NORCAS, стр. 1-6. IEEE, (2019)A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural Networks., , и . NORCAS, стр. 1-6. IEEE, (2019)28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block., , и . MIXDES, стр. 105-110. IEEE, (2016)Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion., , , и . ISCAS (4), стр. 838-841. IEEE, (2001)Extreme low-voltage floating-gate CMOS transconductance amplifier., , , , и . ISCAS (1), стр. 37-40. IEEE, (2001)Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers., , , , и . ISCAS (1), стр. 345-348. IEEE, (2003)