( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Cone-based placement for field programmable gate arrays.

, , и . IET Comput. Digit. Tech., 5 (1): 49-62 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Pritha Mahata

Abhishek Banerjee

Prabuddha Banerjee

Mita Banerjee

Nandakishore Banerjee

 

Другие публикации лиц с тем же именем

Floorplanning for Partial Reconfiguration in FPGAs., , и . VLSI Design, стр. 125-130. IEEE Computer Society, (2009)Cone-based placement for field programmable gate arrays., , и . IET Comput. Digit. Tech., 5 (1): 49-62 (2011)Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography., , и . VLSI-SoC, стр. 1-6. IEEE, (2022)Floorplanning in Modern FPGAs., , и . VLSI Design, стр. 893-898. IEEE Computer Society, (2007)Fast FPGA Placement using Space-filling Curve., , , , и . FPL, стр. 415-420. IEEE, (2005)Threshold voltage modeling of Gaussian-doped Dual work function Material Cylindrical Gate-all-around (CGAA) MOSFET considering the effect of temperature and fixed interface trapped charges., и . Microelectron. J., (2022)Stitch-avoiding Global Routing for Multiple E-Beam Lithography., , , и . VLSID, стр. 138-143. IEEE, (2022)Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography., , и . ICCD, стр. 411-414. IEEE Computer Society, (2017)Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification., , и . ISVLSI, стр. 212-217. IEEE, (2019)An efficient and effective analytical placer for FPGAs., , и . DAC, стр. 10:1-10:6. ACM, (2013)