Author of the publication

Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processor.

, , , and . ICECS, page 243-246. IEEE, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

On the computation of the prime factor DST., , , and . Signal Process., 42 (3): 231-236 (1995)High-performance FPGA implementations of the cryptographic hash function JH., , , and . IET Comput. Digit. Tech., 7 (1): 29-40 (2013)Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path., , and . J. Supercomput., 39 (3): 251-271 (2007)Ultra High Speed SHA-256 Hashing Cryptographic Module for IPSec Hardware/Software Codesign., , , , , and . SECRYPT, page 309-313. SciTePress, (2010)A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard., , , and . ISCAS (1), page 472-475. IEEE, (2005)An efficient VLSI implementation for forward and inverse wavelet transform for JPEG2000., , , and . DSP, page 233-236. IEEE, (2002)Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures., , , , and . ICECS, page 285-288. IEEE, (2001)Hardware and Power Requirements of Self-checking circuits., , , , , and . ICECS, page 1655-1658. IEEE, (1999)A unified evaluation framework for coarse grained reconfigurable array architectures., , , and . Conf. Computing Frontiers, page 161-172. ACM, (2007)Compiler assisted architectural exploration for coarse grained reconfigurable arrays., , , and . ACM Great Lakes Symposium on VLSI, page 164-167. ACM, (2007)