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Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design.

, , и . DAC, стр. 533-538. IEEE, (2007)

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Vittalapura Jayaram

Jayaram Dadda

Vinay Suryaprakash

Vinay Bettadapura

Vinay Vijayakumar

 

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Timing-based delay test for screening small delay defects., , и . DAC, стр. 320-325. ACM, (2006)A Cognitive Brain-Computer Interface for Patients with Amyotrophic Lateral Sclerosis., , , , , , , , , и . SMC, стр. 3187-3191. IEEE, (2015)Frequency peak features for low-channel classification in motor imagery paradigms., , и . NER, стр. 321-324. IEEE, (2017)Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design., , и . DAC, стр. 533-538. IEEE, (2007)A novel framework for faster-than-at-speed delay test considering IR-drop effects., , и . ICCAD, стр. 198-203. ACM, (2006)Supply Voltage Noise Aware ATPG for Transition Delay Faults., , и . VTS, стр. 179-186. IEEE Computer Society, (2007)A machine learning approach to taking EEG-based brain-computer interfaces out of the lab.. University of Tübingen, Germany, (2018)Brain-computer interfacing in amyotrophic lateral sclerosis: Implications of a resting-state EEG analysis., , , , , , , , , и . EMBC, стр. 6979-6982. IEEE, (2015)Interpretable Riemannian Classification in Brain-Computer Interfacing., , и . GBCIC, Verlag der Technischen Universitaet Graz, (2019)MOABB: Trustworthy algorithm benchmarking for BCIs., и . CoRR, (2018)