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Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Initial Evaluation of Multimedia Extensions on VLIW Architectures., and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 403-412. Springer, (2004)Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units., , , , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 88-97. Springer, (2004)Hardware transactional memory with software-defined conflicts., , , , , , , and . ACM Trans. Archit. Code Optim., 8 (4): 31:1-31:20 (2012)Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Parallel Computer Architecture., , , and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 537-538. Springer, (2000)Topic 15+20: Multimedia and Embedded Systems., , , and . Euro-Par, volume 2150 of Lecture Notes in Computer Science, page 651-652. Springer, (2001)Memory Access Synchronization in Vector Multiprocessors., , and . CONPAR, volume 854 of Lecture Notes in Computer Science, page 414-425. Springer, (1994)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications., , , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)