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Disambiguation of "Shinohara, Hirofumi"

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A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture.

, , and . ICCD, page 202-205. IEEE Computer Society, (1993)

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Kenichi Shinohara

Hirofumi Ishihara

Hirofumi Hosokawa

Hirofumi Ueda

Hirofumi Kumazawa

 

Other publications of authors with the same name

A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance., , , , and . ESSCIRC, page 513-516. IEEE, (2022)A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology., , , , , , , , , and 15 other author(s). COOL Chips, page 1-3. IEEE Computer Society, (2014)60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations., , , , , and . ESSCIRC, page 317-320. IEEE, (2012)A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture., , and . ICCD, page 202-205. IEEE Computer Society, (1993)Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology., , , , , and . ISLPED, page 15-20. ACM, (2008)12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains., , , , , and . ESSCIRC, page 191-194. IEEE, (2011)A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement., , , , , and . VLSI-DAT, page 1-4. IEEE, (2022)Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability., , , , , , , , and . ICCAD, page 398-405. IEEE Computer Society, (2005)A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die., , , , , , , , , and 7 other author(s). ISSCC, page 488-617. IEEE, (2007)Variation-aware subthreshold logic circuit design., , , , , and . ASICON, page 1-4. IEEE, (2013)