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Disambiguation of "Kumar, Shasi"

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A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS.

, , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 757-766 (2011)

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Podiyanachari Santhosh Kumar

Rohini Kumar

Aditya Kumar

Pardeep Kumar

Mahmoud Kumari Zadeh

 

Other publications of authors with the same name

A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 757-766 (2011)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 46 (1): 184-193 (2011)An IA-32 processor with a wide voltage operating range in 32nm CMOS., , , , , , , , , and 9 other author(s). Hot Chips Symposium, page 1-37. IEEE, (2012)A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip., , , , , , , , and . VLSI Design, page 292-297. IEEE Computer Society, (2012)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)Modified hill-top algorithm based maximum power point tracking for solar PV module., , , , , and . ISIE, page 1801-1806. IEEE, (2012)