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Fault-tolerant Quantum Implementation of 1-bit and 4-bit Comparator Circuit using Clifford+T-group., , и . ISED, стр. 1-6. IEEE, (2019)A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs., , , и . VLSI-SoC, стр. 122-127. IEEE, (2015)Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability., , и . J. Electron. Test., 22 (2): 125-142 (2006)Binary decision diagram-based synthesis technique for improved mapping of Boolean functions inside memristive crossbar-slices., , , , , и . IET Comput. Digit. Tech., 15 (2): 112-124 (2021)Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra., , , , , , , и . IAIT, стр. 23:1-23:6. ACM, (2023)Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m)., , и . VLSI Design, стр. 479-484. IEEE Computer Society, (2007)A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips., , , и . Asian Test Symposium, стр. 25-30. IEEE Computer Society, (2012)A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips., , и . DDECS, стр. 122-128. IEEE Computer Society, (2014)Optimization of DC-DC Power Converter Design with Second Generation HiSIM_HV Model., , , , , , и . ISDCS, стр. 1-5. IEEE, (2019)C-testable S-box implementation for secure advanced encryption standard., , , и . IOLTS, стр. 210-211. IEEE Computer Society, (2009)