Author of the publication

An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit.

, , , and . VLSI Circuits, page 153-154. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

BAG2: A process-portable framework for generator-based AMS circuit design., , , , , , and . CICC, page 1-8. IEEE, (2018)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET., , , , , , , , , and 21 other author(s). A-SSCC, page 285-288. IEEE, (2018)BAG: A Process-Portable Framework for Generator-based AMS Circuit Design., , , and . CICC, page 1-20. IEEE, (2019)A fully-integrated 10.5µW miniaturized (0.125mm2) wireless neural sensor., , , , and . VLSIC, page 72-73. IEEE, (2012)A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2019)Design of Energy- and Cost-Efficient Massive MIMO Arrays., , , , , , , , , and 3 other author(s). Proc. IEEE, 104 (3): 586-606 (2016)A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 53 (12): 3613-3627 (2018)An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit., , , and . VLSI Circuits, page 153-154. IEEE, (2018)A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit., , , and . ESSCIRC, page 273-276. IEEE, (2019)A scalable massive MIMO array architecture based on common modules., , , , , , and . ICC Workshops, page 1310-1315. IEEE, (2015)