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Disambiguation of "Shelar, Rupesh S."

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An efficient technology mapping algorithm targeting routing congestion under delay constraints.

, , , and . ISPD, page 137-144. ACM, (2005)

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Other publications of authors with the same name

A predictive distributed congestion metric with application to technology mapping., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (5): 696-710 (2005)An efficent clustering algorithm for low power clock tree synthesis.. ISPD, page 181-188. ACM, (2007)An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops.. FPGA, page 323. ACM, (2020)Delay-optimal simultaneous technology mapping and placement with applications to timing optimization., , and . ICCAD, page 101-106. IEEE Computer Society, (2008)Parameterized Reusable Component Library Methodology., , and . EUROMICRO, page 1410-1415. IEEE Computer Society, (2000)An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors.. ISPD, page 141-148. ACM, (2009)An efficient technology mapping algorithm targeting routing congestion under delay constraints., , , and . ISPD, page 137-144. ACM, (2005)Impact of local interconnects on timing and power in a high performance microprocessor., and . ISPD, page 145-152. ACM, (2010)Decomposition of Finite State Machines for Area, Delay Minimization., , and . ICCD, page 620-625. IEEE Computer Society, (1999)An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis., and . ASP-DAC/VLSI Design, page 87-92. IEEE Computer Society, (2002)