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Specification and Simulation of Real Time Concurrent Systems Using Standard SDL Tools., , и . SDL Forum, том 2708 из Lecture Notes in Computer Science, стр. 203-217. Springer, (2003)An error simulation based approach to measure error coverage of formal properties., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 53-58. ACM, (2002)Concrete Impact of Formal Verification on Quality in IP Design and Implementation., , , и . ISQED, стр. 38-43. IEEE Computer Society, (2001)On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling., , и . MTV, стр. 127-132. IEEE Computer Society, (2005)A Verification Methodology for Reconfigurable Systems., , , , , , , и . MTV, стр. 85-90. IEEE Computer Society, (2004)On the Use of a High-Level Fault Model to Check Properties Incompleteness., , , , и . MEMOCODE, стр. 145-152. IEEE Computer Society, (2003)Modeling Flexible Real Time Systems with Preemptive Time Petri Nets., , , и . ECRTS, стр. 279-286. IEEE Computer Society, (2003)A 1000X speed up for properties completeness evaluation., , , , , , , и . HLDVT, стр. 18-22. IEEE Computer Society, (2002)Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling., , и . MEMOCODE, стр. 239-240. IEEE Computer Society, (2005)Predicting Timeliness of Reactive Systems under Flexible Scheduling., , и . ISADS, стр. 125-130. IEEE Computer Society, (2003)