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Optimizing geographically distributed timed cosimulation by hierarchically grouped messages.

, and . CODES, page 100-104. ACM, (1999)

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DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture., , and . HPCA, page 25-36. IEEE Computer Society, (2014)Energy-efficient partitioning of hybrid caches in multi-core architecture., and . VLSI-SoC, page 1-6. IEEE, (2014)Aging Gracefully with Approximation., , , , , and . ISCAS, page 1-5. IEEE, (2019)Rate Assignment for Embedded Reactive Real-Time Systems., and . EUROMICRO, page 10237-. IEEE Computer Society, (1998)Architectures and algorithms for user customization of CNNs., , , , , , , , , and 1 other author(s). ASP-DAC, page 540-547. IEEE, (2018)Coarse-grained reconfigurable architecture for multiple application domains: a case study., , , , , , and . ICHIT, volume 321 of ACM International Conference Proceeding Series, page 546-553. ACM, (2009)Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design., , and . FPGA, page 247. ACM, (1999)Critical-path-aware high-level synthesis with distributed controller for fast timing closure., and . ACM Trans. Design Autom. Electr. Syst., 19 (2): 16:1-16:29 (2014)Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems., and . CASES, page 230-237. ACM, (2004)Entry control in network-on-chip for memory power reduction., , and . ISLPED, page 171-176. ACM, (2008)