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Live demonstration: Real-time image processing on ASPA2 vision system.

, , , and . ISCAS, page 1989. IEEE, (2011)

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Live demonstration: Real-time image processing on ASPA2 vision system., , , and . ISCAS, page 1989. IEEE, (2011)A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology., , and . ECCTD, page 193-196. IEEE, (2009)A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array., and . CICC, page 1-4. IEEE, (2013)An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology., and . ISCAS, page 4257-4260. IEEE, (2010)Architecture and design of a programmable 3D-integrated cellular processor array for image processing., and . VLSI-SoC, page 349-353. IEEE, (2011)Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fps., , , , and . ICECS, page 324-327. IEEE, (2012)A processor element for a mixed signal cellular processor array vision chip., , and . ISCAS, page 1564-1567. IEEE, (2011)ASPA: Focal Plane digital processor array with asynchronous processing capabilities., and . ISCAS, page 1592-1595. IEEE, (2008)Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array., and . ECCTD, page 84-87. IEEE, (2007)Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing., and . ISCAS, IEEE, (2006)