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On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function.

, , , , and . SECRYPT, page 270-275. SciTePress, (2012)

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On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function., , , , and . SECRYPT, page 270-275. SciTePress, (2012)A Novel Constant-Time Fault-Secure Binary Counter., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 742-749. Springer, (2004)A novel coarse-grain reconfigurable data-path for accelerating DSP kernels., , , , and . FPGA, page 252. ACM, (2004)Power aware data type refinement on the HIPERLAN/2., , , , , and . ICECS, page 216-219. IEEE, (2003)A high performance data-path to accelerate DSP kernels., , , , and . ICECS, page 495-498. IEEE, (2004)Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs., , , , , and . Journal of Circuits, Systems, and Computers, 25 (4): 1650032:1-1650032:26 (2016)Optimising the SHA-512 cryptographic hash function on FPGAs., , , and . IET Comput. Digit. Tech., 8 (2): 70-82 (2014)A high-performance data path for synthesizing DSP kernels., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1154-1162 (2006)Task graph mapping and scheduling on heterogeneous architectures under communication constraints., , , , and . SAMOS, page 239-244. IEEE, (2017)An reconfigurable multiplier in GF(2m) for elliptic curve cryptosystem., , and . ICECS, page 699-702. IEEE, (2003)