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Disambiguation of "Guarnieri, Valerio"

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Mutation analysis for SystemC designs at TLM.

, , , , , , , and . LATW, page 1-6. IEEE, (2011)

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Walter Guarnieri

Valerio Ketmaier

Filippo Guarnieri

Valerio Cosentino

Valerio Maggio

 

Other publications of authors with the same name

Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis., , and . VLSI-SoC, page 61-66. IEEE, (2010)On the reuse of RTL assertions in SystemC TLM verification., , , , , , , , and . LATW, page 1-6. IEEE, (2014)A cross-level verification methodology for digital IPs augmented with embedded timing monitors., , , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)On the Reuse of TLM Mutation Analysis at RTL., , , , , , , , and . J. Electron. Test., 28 (4): 435-448 (2012)Efficient implementation and abstraction of systemc data types for fast simulation., , , , and . FDL, page 1-7. IEEE, (2011)An optimized CLP-based technique for generating propagation sequences., , , and . EWDTS, page 25-29. IEEE Computer Society, (2008)Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs., , and . HLDVT, page 105-112. IEEE Computer Society, (2010)Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis., , , , and . MTV, page 76-81. IEEE Computer Society, (2012)Reusing RTL Assertion Checkers for Verification of SystemC TLM Models., , , , , , , , and . J. Electron. Test., 31 (2): 167-180 (2015)A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection., , , , , , , , and . Sensors, 15 (7): 17076-17088 (2015)