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Fully-Fusible Convolutional Neural Networks for End-to-End Fused Architecture with FPGA Implementation., , , , and . ICECS, page 1-5. IEEE, (2023)Side-Channel Attacks on Triple Modular Redundancy Schemes., , , and . ATS, page 79-84. IEEE, (2021)An External Test Approach for Network-on-a-Chip Switches., , and . ATS, page 437-442. IEEE, (2006)Enhancing Fault Resilience of QNNs by Selective Neuron Splitting., , , , and . AICAS, page 1-5. IEEE, (2023)From RTL Liveness Assertions to Cost-Effective Hardware Checkers., , , and . DCIS, page 1-6. IEEE, (2018)Hierarchical Identification of Untestable Faults in Sequential Circuits., , , and . DSD, page 668-671. IEEE Computer Society, (2007)Fault Diagnosis in Integrated Circuits with BIST., , , , and . DSD, page 604-610. IEEE Computer Society, (2007)Parallel X-fault simulation with critical path tracing technique., , , and . DATE, page 879-884. IEEE Computer Society, (2010)Automated Design Error Localization in RTL Designs., , , , , , , , and . IEEE Des. Test, 31 (1): 83-92 (2014)RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems., , , , , , , , , and 8 other author(s). CoRR, (2019)