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A Unified Framework for Design Validation and Manufacturing Test.

, , and . ITC, page 875-884. IEEE Computer Society, (1996)

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Research in Reliable VLSI Architectures at the University of Illinois.. FJCC, page 890-893. IEEE Computer Society, (1986)Design of Test Pattern Generators for Built-In Test., , and . ITC, page 315-319. IEEE Computer Society, (1984)A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems., and . ISLPED, page 391-396. IEEE/ACM, (2011)Forward Recovery Using Checkpointing in Parallel Systems., , and . ICPP (1), page 272-275. Pennsylvania State University Press, (1990)Abstraction of data path registers for multilevel verification of large circuits., , , and . Great Lakes Symposium on VLSI, page 11-14. IEEE, (1994)Design and evaluation of fault tolerance techniques for highly parallel architectures.. Great Lakes Symposium on VLSI, IEEE, (1991)An oscillation-based test structure for timing information extraction., , , and . VTS, page 74-79. IEEE Computer Society, (2012)Average Interconnection Length and Interconnection Distribution Based on Rent's Rule., and . DAC, page 574-577. ACM Press, (1989)A Novel Approach to Accurate Timing Verification Using RTL Descriptions., and . DAC, page 638-641. ACM Press, (1989)Delay Defect Diagnosis Methodology Using Path Delay Measurements., , and . IEICE Trans. Electron., 98-C (10): 991-994 (2015)