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Prediction router: Yet another low latency on-chip router architecture.

H. Matsutani, M. Koibuchi, H. Amano, and T. Yoshinaga. HPCA, page 367-378. IEEE Computer Society, (2009)

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Michihiro Saito

Other publications of authors with the same name

The Impact of Application Mapping on Non-Random and Random Network Topologies.Y. Hu, and M. Koibuchi. ISPA/BDCloud/SocialCom/SustainCom, page 16-25. IEEE, (2019)Designing High-Performance Interconnection Networks with Host-Switch Graphs.R. Yasudo, M. Koibuchi, K. Nakano, H. Matsutani, and H. Amano. IEEE Trans. Parallel Distributed Syst., 30 (2): 315-330 (2019)A link removal methodology for Networks-on-Chip on reconfigurable systems.D. Wang, H. Matsutani, H. Amano, and M. Koibuchi. FPL, page 269-274. IEEE, (2008)SINET5: A low-latency and high-bandwidth backbone network for SDN/NFV Era.T. Kurimoto, S. Urushidani, H. Yamada, K. Yamanaka, M. Nakamura, S. Abe, K. Fukuda, M. Koibuchi, H. Takakura, S. Yamada and 1 other author(s). ICC, page 1-7. IEEE, (2017)AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation.A. Ahmed, D. Fujiki, H. Matsutani, M. Koibuchi, and H. Amano. NOCS, page 6:1-6:8. IEEE, (2018)Scalable Low-Latency Inter-FPGA Networks.K. Pham, T. Nguyen, H. Yamaguchi, Y. Urino, and M. Koibuchi. IPDPS, page 234-245. IEEE, (2022)A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks.H. Matsutani, M. Koibuchi, and H. Amano. PDCS, page 24-31. ISCA, (2006)Message from the Organizers: CANDAR 2022.J. Bordim, M. Koibuchi, S. Fujita, and K. Nakano. CANDAR, page viii. IEEE, (2022)Layout-conscious random topologies for HPC off-chip interconnects.M. Koibuchi, I. Fujiwara, H. Matsutani, and H. Casanova. HPCA, page 484-495. IEEE Computer Society, (2013)Efficient Scheduling Algorithms on Bandwidth Reservation Service of Internet Using Metaheuristics.T. Hiroyasu, K. Kawasaki, M. Koibuchi, S. Urushidani, M. Miki, and M. Yoshimi. ISDA, page 683-688. IEEE Computer Society, (2009)

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Disambiguation of "Koibuchi, Michihiro"

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Prediction router: Yet another low latency on-chip router architecture.

Please choose a person to relate this publication to

Michihiro Saito

Other publications of authors with the same name

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Disambiguation of "Koibuchi, Michihiro"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Prediction router: Yet another low latency on-chip router architecture.

Please choose a person to relate this publication to

Michihiro Saito

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
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Prediction router: Yet another low latency on-chip router architecture.