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Disambiguation of "Xie, Jiafeng"

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Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform.

, , , and . FCCM, page 114-120. IEEE, (2023)

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Jiafeng Zhang

Mingliang Xie

Qian Xie

Zhenwei Xie

Lan Xie

 

Other publications of authors with the same name

Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity., and . FPGA, page 187. ACM, (2019)Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography., , , and . IEEE Trans. Emerg. Top. Comput., 10 (2): 1222-1228 (2022)Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography., , , and . CODES+ISSS, page 5-6. IEEE, (2022)Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform., , and . FPGA, page 156. ACM, (2022)AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQC., , , and . ICFPT, page 6. IEEE, (2023)Novel Implementation of High-Performance Polynomial Multiplication for Unified KEM Saber based on TMVP Design Strategy., and . ISQED, page 1-8. IEEE, (2023)Weibo-MEL, Wikidata-MEL and Richpedia-MEL: Multimodal Entity Linking Benchmark Datasets., , , , and . CCKS, volume 1466 of Communications in Computer and Information Science, page 315-320. Springer, (2021)Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method., , and . ISCAS, page 1-5. IEEE, (2019)Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing., , and . ISCAS, page 89-92. IEEE, (2012)FEED: A Chinese Financial Event Extraction Dataset Constructed by Distant Supervision., , , , and . IJCKG, page 45-53. ACM, (2021)